cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 1/9 MTB30N06V8 cystek product specification n -channel logic level enha ncement mode power mosfet MTB30N06V8 bv dss 60v i d 6.8a 24m v gs =10v, i d =6.8a r dson(typ) features ? low gate charge ? simple drive requirement ? pb-free lead plating package equivalent circuit outline MTB30N06V8 dfn3 3 v gs =4.5v, i d =4a 28m g gate d drain s source pin 1 absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage v ds 60 gate-source voltage v gs 20 v continuous drain current @ t c =25 c, v gs =10v 13 continuous drain current @ t c =100c, v gs =10v 8.2 continuous drain current @ t a =25 c, v gs =10v 6.8 continuous drain current @ t a =100c, v gs =10v i d 4.3 pulsed drain current *1 i dm 30 a avalanche energy @ l=0.1mh, i d =20a, v dd =30v e as 40 mj total power dissipation @t c =25 9 total power dissipation @t a =25 p d 2.5 w operating junction and storage te mperature range tj, tstg -55~+150 c note : *1. pulse width limited by maximum junction temperature. *2. duty cycle 1%. *3. surface mounted on a 1 in2 pad of fr-4 board with 2oz copper, t 10s.
cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 2/9 MTB30N06V8 cystek product specification thermal data parameter symbol value unit thermal resistance, junction-to-case, max r th,j-c 13.8 c/w thermal resistance, junction-to-ambient, max r th,j-a 50 * c/w * surface mounted on a 1 in2 pad of fr-4 board with 2oz copper, t 10s. electrical characteristics (tj=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss 60 - - v v gs =0v, i d =250 a v gs(th) 1 1.8 3 v v ds =v gs , i d =250 a i gss - - 100 na v gs =20v, v ds =0v - - 1 v ds =60v, v gs =0v i dss - - 25 a v ds =48v, v gs =0v, tj=125 - 24 35 v gs =10v, i d =6.8a *r ds(on) - 28 40 m v gs =4.5v, i d =4a *g fs - 18 - s v ds =5v, i d =6.8a dynamic ciss - 1546 - coss - 59 - crss - 42 - pf v ds =30v, v gs =0, f=1mhz t d(on) - 16 - t r - 7.5 - t d(off) - 47 - t f - 17 - ns v ds =30v, i d =1a, v gs =10v, r g =6 ? qg - 18 - qgs - 5.2 - qgd - 6.3 - nc v ds =30v, i d =6.8a, v gs =10v, *pulse test : pulse width 300 s, duty cycle 2% source drain diode symbol min. typ. max. unit test conditions *i s - - 6.8 *i sm - - 30 a *v sd - 0.8 1.3 v i s =6.8a,v gs =0v *t rr - 46 - ns q rr - 42 - nc i s =6.8a,v gs =0v, di/dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 3/9 MTB30N06V8 cystek product specification typical characteristics typical output characteristics 0 5 10 15 20 25 30 01234 5 brekdown voltage vs ambient temperature 50 60 70 80 90 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , drain-source breakdown voltage (v) i d =250 a, v gs =0v 10v,9v,8v,7v,6v v ds , drain-source voltage(v) i d , drain current (a) v gs =4v v gs =3v v gs =2v static drain-source on-state resistance vs drain current 10 100 1000 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =2.5v v gs =4.5v v gs =3v v gs =10v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 024681 i dr , reverse drain current(a) v sd , source-drain voltage(v) 0 tj=25c tj=150c v gs =0v static drain-source on-state resistance vs gate-source voltage 0 40 80 120 160 200 024681 0 drain-source on-state resistance vs junction tempearture 0 20 40 60 80 -60 -20 20 60 100 140 180 tj, junction temperature(c) r ds(on) , static drain-source on-state resistance(m) v gs =10v, i d =6.8a v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =6.8a
cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 4/9 MTB30N06V8 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 10000 0.1 1 10 100 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 1 1.2 1.4 1.6 1.8 2 2.2 2.4 -60 -20 20 60 100 140 tj, junction temperature(c) v gs(th) , threshold voltage(v) i d =250 a forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) ta=25c pulsed v ds =5v gate charge characteristics 0 2 4 6 8 10 048121620 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =6.8a v ds =48v v ds =30v v ds =12v maximum safe operating area 0.01 0.1 1 10 100 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) t a =25c, tj=150c v gs =10v, ja =50c/w single pulse dc 10ms 100ms r dson limited 10 s 100 s 1ms maximum drain current vs case temperature 0 1 2 3 4 5 6 7 8 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =10v
cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 5/9 MTB30N06V8 cystek product specification typical characteristics(cont.) single pulse power rating, junction to ambient (note on page 2) 0 10 20 30 40 50 0.01 0.1 1 10 100 pulse width(s) power (w) t j(max) =150c t a =25c ja =50c/w transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =50c/w
cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 6/9 MTB30N06V8 cystek product specification recommended soldering footprint unit : mm ordering information device package shipping marking MTB30N06V8 dfn3 3 (pb-free lead plating package) 3000 pcs / tape & reel b30n06
cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 7/9 MTB30N06V8 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 8/9 MTB30N06V8 cystek product specification recommended wave soldering condition product peak temperature soldering time pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3 c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak temperature(tp) 10-30 seconds 20-40 seconds ramp down rate 6 c/second max. 6 c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of t he package, measured on the package body surface.
spec. no. : c699v8 issued date : 2012.03.20 revised date : 2012.03.26 page no. : 9/9 cystech electronics corp. MTB30N06V8 cystek product specification dfn3 3 dimension marking: date code s s s g d d d d 3484 b30 n06 8-lead dfn3 3 plastic package cystek package code: v8 *: typical inches millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.0276 0.0354 0.70 0.90 e 0.1181 0.1260 3.00 3.20 a1 0.0000 0.0197 0.00 0.50 e1 0.0531 0.0610 1.35 1.55 b 0.0094 0.0138 0.24 0.35 e 0.0256 bsc 0.65 bsc c 0.0039 0.0079 0.10 0.20 h 0.1260 0.1339 3.20 3.40 d 0.1280 0.1339 3.25 3.40 l 0.0118 0.0197 0.30 0.50 d1 0.1201 0.1280 3.05 3.25 l1 0.0039 0.0079 0.10 0.20 d2 0.0945 0.1024 2.40 2.60 l2 0.0445 ref 1.13 ref notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing specification or packing method, please c ontact your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitable for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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